Others view: RSA encryption algorithm ♦ Generalized Lambda distributio.. ♦ 2-3-4 tree ♦ Dot-Bracket Notation ♦ Applet screen shoot license ♦ Braille code ♦ rss.xml ♦ rutherford ♦ Welcome ♦ Reversal potential ♦

As a rule, the counter counts the number of fronts (0 to 1) or usually the number of tails (1 to 0) of the input signal. The counter has limited capacity and starts counting from zero again (rolls over) after counting till number, defined by the counter design. Counters can be cascaded; connecting output of the highest binary digit as the input signal of the second counter creates a complex counter that counts till number that is a product of the maximal capacities of the both counters involved. The simplest counter of capacity 2 (0, 1 then roll over) is a single T flip-flop. A typical binary counter is built from such flip-flops, cascading sufficient number of them to get the required capacity.

If the used flip-flops respond to the tail (rather than front) of the pulse in the input, the counter that is built from them counts in a usual binary system. A counter with flip-flops that respond to the front would not count as expected: from the state 0000, the onset of the first pulse would propagate through the all counter, resulting 1111. Such device still works as a usable counter but it count in inverted system. Hence most of integrated circuits that implement a T flip flop react to the tail of the input signal. Typically an integrated circuit would feature four flip-flops that are already connected to make a counter. Such four digit counters can also be cascaded.

After powering on, the counter would start counting from random number. To count from zero (and also reset the counter to zero at any time), a counter usually features an additional reset input. The reset input is also required to build counters that count till arbitrary number like 6 or 10, rather than to they maximal capacity of where n is the number of flip flops.

While the maximal number (exclusive) till that the binary counter could count is , many counters need to count till some different value. For instance, counters that are for humans to read, usually count in decimal rather than binary system (decade counters), rolling over to 0 (and possibly incrementing next decimal digit) after exceeding 9.

Such counters are easy to build from the binary counter with capacity that is sufficient to hold the maximal required value, supplementing it by the AND logic gate. The inputs of this gate are connected to the counter outputs that take the value "1" when the counter exceeds its required capacity and must roll over.

For instance, to build a decade counter, we need four binary digits (as three would be able to count at most till 111 = 7 decimal). Now, the first "illegal" value that must reset the counter to zero is 10 decimal = 1010 binary. Hence we need a two input AND gate with these inputs connected to the second (representing 2) and the highest (representing 8) binary digits of the counter. The output of this AND gate is connected to the counter "reset" input and sets it back to 0. So the value 1010 only appears very transiently and not as counted value; a human sees the counter state changing in the sequence 012345678901234 (..).

One may ask, should not we use a more complex gate to reset from say 1100 state that is also above nine (1001) and our AND element would not generate any reset signal? This is not necessary as

- the counter always counts from zero up by the increment of one
- replacing any zero by one only increases the value of the binary number.

From these two rules are obvious that the value with 1's in all connected inputs of the AND gate and 0's in all inputs that are not connected comes before any value that would have additional 1's in other outputs, exceeding the required limit of the counter. If the counter gets the value beyond the limit after first powering it on, it counts at most till its "native" binary limit (15 for 4 digit counter) and then rolls over anyway, becoming a decade counter. Counters are also frequently set to zero by providing a short duration reset signal immediately after powering on.

As the second example, let's build the counter for tens of minutes for the electronic clock. It must count from 0 to five, so three digits would be enough. The roll over value, decimal six (binary 0110) requires the AND gate with inputs connected to the second ("2") and third ("4") outputs of the counter.

Counters are also frequently used just to lower the frequency of the periodic input signal rather than to count the exact number of signals in the input. For instance, the quartz resonator (crystal oscillator) of the electronic watch often runs at frequency of 32768 Hz. It is connected to the input of the fifteen digit binary counter that then changes the value of the highest digit with the frequency of 1 Hz (=32768), usually the first frequency interesting when constructing a watch. If the watch only shows minutes (no seconds), the 1 Hz output is connected to the input of the divider by 60 that we can build by joining previously described 0 to 9 and 0 to 5 counters together and then count signals with the frequency of 1/60 Hz (minutes).

Frequency dividers can produce highly accurate (while not absolutely precise) frequencies from any input of the fixed sufficiently high frequency. For instance, it is not possible to generate absolutely precise frequencies for musical scale, because musical half-tones differ from each other by , the irrational number. Instead, the highly accurate leading generator of the electronic musical instrument runs at very high frequency that is supplied to the inputs of 12 dedicated dividers, one per half-tone. This produces arbitrary accurate outputs for the single octave that must be the highest octave supported by the instrument. Frequencies for the lower octave are exactly two times lower than frequencies of the adjacent higher octave so they can be easily obtained with a single T flip flop, dividing by two. Radio equipment and computer motherboard chips may also use this method to get the specified required frequency.

During its work the "classic" design (described above) transiently shows incorrect output values. These values last for a very short time and are not visible for the human operator. However they can generate unexpected signals in other connected digital circuits. If the counter limit is lowered with AND gate as described above, the counter *must* transiently obtain the value one above the limit, and it must last long enough for the gate to reset the counter. But even "pure" counter that only contains T flip flops generates transient incorrect values as the 1 to 0 changes "ripples" over the counter when the lower sections roll over. For instance, the binary 0111 with not turn instantly into 1000 after getting one more pulse. Instead, the change will gradually propagate from right to left and intermediate values of 011**0**, 01**00** and 0**000** may shortly show up before the final stable **1000** comes out. The visualization on the left shows the simple circuit designed to detect the binary value 10 in the output of the counter. It does detect this combination. However when turning from 11 to 00, the signal LED incorrectly light up for a short time, triggered by the transient 1**0**. To make this incorrect state long enough to notice, a delay element has been added between flip flops. However incorrect signal would appear without any additional delay elements as signal always propagates at limited speed.

Where important, this problem can be solved using Gray code rather than traditional binary representation (in Gray code, only one digit changes value between adjacent numbers). However binary to Gray converter, attached to the output of the simple binary counter how is described in XOR gate article, cannot solve the problem. The output of such converter is not glitch free because the *input* of the converter contains glitches (trash in, trash out)^{[1]}. In order to produce the consistent noise-free output, the counter must count in Gray code directly. In some degree it can also be solved using ring counter or additional synchronization signals to read the counter value only after it is ready.

The ripple wave over digits can be eliminated by implementing design where all flip-flops change state at the same (or near at the same) time rather than having a ripple wave over digits. Such design uses D flip-flopss that have they inverted output connected to the data input. When signal arrives to the synchronization input of such flip-flop, it "flips over", inverting the current state. The simple circuit of AND gates quenches the counting signal for flip-flops that must not change they state when incrementing the current number.

Synchronous counters are more complex. However they are faster and more reliable. Most of the counters that are currently available in the form of the integrated circuits, are synchronous counters.

^{1 }Synthesis Issues