If the number of inputs having logical one is equal to the number of inputs having logical zero, the element keeps the current state. In other words, the gate is capable for hysteresis. It is similar to the small parlament where the members need majority to accept some decision but once the decision is accepted they stick to it if the votes are equal and need majority again to agree on the opposite.
For the element with the two inputs, this means that the input combination 11 turns the element into state 1, combination 00 into state 0 and combinations 10 or 01 leave it in the same state where it has been before.
The truth table of this gate is unusual, as it includes the "no change" cases. For these cases, the element keeps the state as it has been before the change of the input combination. If "no change" combination is the first combination since the element exists, the element obtains and keeps some random state:
|First input||Second input||Output|
C gate is not an universal logic gate: it needs some other element(s) in addition to build a functionally complete logic system.
The two input C gate can be assembled from AND and OR logic gates (invertors are not required). It can also be made more simply if assembled directly from discrete elements as it is possible to use the positive feedback loop inside the OR gate rather than closing it through the AND elements. Such OR element must have the hysteresis similar to the hysteresis of the Schmitt trigger, with voting inputs pulling toward one of the two stable states.
The gate can also be built with more than two inputs. If the number of inputs is odd, there is no "equal number of inputs" case but some "big majority rule" (for instance, only the same value on all three inputs changes the state) can still be used to obtain the hysteresis. This element can also be extended to the Asymmetric C-element where some inputs only have effect the operation in one of the transitions (positive or negative).
Asymmetric C-elements have inputs which only effect the transitioning in one of the directions (0 to 1 or 1 to 0). Depending on the affected transition, they are called either plus input (P or +) or minus inputs (M or -). It still may have C inputs that affect both transitions.
For the element, shown in the example, signal in the inputs C and P is sufficient to bring the element in the active (logical 1) state: M does not count. However when the element is in the active state, the M input can keep it in this state regardless of the level in other inputs: as P does not count, C alone cannot make a majority.
This type of element, proposed by David E. Muller, was first used on ILLIAC II supercomputer, built in 1962. It is usually used in asynchronous logic where the parts are largely autonomous and not governed by a clock circuit or global clock signal. Its typical role is to synchronize several independent processes, making the output independent on the delay differences between various parts of the system. C gate can also be used as a majority gate or as a toggle switch.
Theoretical biologists are also interested in these elements as they may be used to describe the pairwise gene interaction, reconstructing the gene interaction network in the cell. This method uses the gene-expression data from microarray experiments as input.