A trigger (also called flip-flop or latch) is a device with two stable states, capable to store information. Triggers can be directly constructed from logic gates in cases when gate output is indirectly (through other gates) connected to its own input, creative positive feedbacks.
The simplest memory cell (R-S trigger) is a ring of the two inverting gates (usually NAND but can also be NOR). It uses the second input of the gates to set the trigger into one of the two possible stable states. The two inputs that control the state are usually labelled R and S (Reset and Set).
This examples shows the flip-flop, constructed from two OR and two NOT elements. A similar device can be made from two AND and two NOT elements, but its inputs would be inverted (1 means inacative and 0 forces the trigger to change the state). Triggers, based on a ring of NOT elements, frequently have two outputs: direct (where the LED is connected in the diagram) and inverted. In our case, the inverted output would be the output of the bottom NOT element. You can notice this by observing its state (elements forming 1 on the output are highlighted in red).
Important extension of the R-S trigger is to add the third, control signal (C). Such a device (synchronized or clocked R-S trigger) only responds to signals on R and S inputs only if level 1 is present on the input C. Zero at this input "cuts out" R and S signals from the ring, making them to have no effect. A synchronized RS trigger is seldom used by itself, but it is an important step of evolution toward a D trigger. As most of other typical circuits, the synchronized RS trigger can be build in many similar but different ways; in our example we cut the R and S signals with additional AND elements. This device is also called a clocked RS latch.
D flip-flop (or D latch) has data input to set the state and synchronization input to allow setting this state. When level 1 is present in the synchronization input, D trigger state follows the level of the data input. A zero at the synchronization input turns the trigger into "storing" mode: it remembers the current state and no longer cares about the level at the D input. Hence, the D triger is capable to receive and store binary data more directly. As a single trigger can only store one bit, D triggers are frequently grouped together. Four triggers can store a single decimal (or hexadecimal) digit, and this number is common in many chips with a low level of integration.
When multiple bits (stored in the multiple triggers) make some large piece of information (like a character or digit), data are usually written into all triggers at the same time. Hence the synchronization inputs should be connected together. When the triggers are implemented in a single chip, it frequently has only one synchronization input, shared by all triggers in the chip. Such group of triggers with a single shared synchronization input is also called a register.
Many important applications of the D trigger require to accept data from the D input in response to the 0 to 1 change of the synchronization signal and be insensitive again when this signal stays at level 1 for the longer time. This allows to build counters and shift registers, as described below.
One of the obvious ways to use this flip-flop is to build a shift register, a main element of a ring counter. As a flip-flop takes the value from the input D (in response to the control signal), a shift register can be easily created by connecting the output of the flip-flop to the input D of the next flip-flop. The benefit of this circuit is that no changes need to propagate over the whole circuit upon arrival of the shift signal: only the state of the adjacent node is important. The synchronization (C) inputs are just connected together.
The T flip-flop changes its state into the opposite when the signal level at its counting input (T) changes from 0 to 1. Hence the trigger is "counting" the 0 to 1 drops in a binary system (0, then 1, then overflow and hence 0 again). This seems not particulary useful, but T triggers can be connected into a chain to count any number of pulses, making them an important part of digital electronics. As it is often necessary to reset the counters, a T trigger usually also has the resent input (R) that works as an input of the RS trigger. When multiple triggers are implemented in the chip, they usually share the single reset input. A T flip-flop is an important component of binary counter.
Unlike the previous flip-flops, a T trigger is a pulse device that cannot be easily represented without a delay line concept (unless we assume that the signal is delayed for some short time inside the logic gates themselves). In general, at least two delay lines are required for the normal operation. The first line (together with AND and NOT elements) forms short pulses on front of the counting (clock) signal. Without the helper circuit, the flip flop would not operate properly if you keep the Count button depressed for too long. The second line ensures reliable change of the current state into the opposite state. The circuit is basically a D trigger where output is connected to the input through an inverter, forcing the flip flop to change the state every time the synchronization signal arrives. However, the synchronization signal, if permanently present, would immediately ask it to take the "opposite" state again, resulting either generation or even unpredictable behavior. Delay elements ensure the stable, predictable transition into the opposite state.
While delay elements or some analogs of them are necessary, the delay duration should be as short as possible as it restricts the minimal duration of the signal that is still capable to change the trigger state into the opposite state.
The flip-flop, pictured above, changes state at the beginning (onset) of the input signal (when level there raises from 0 to 1). This seems logical for the isolated flip-flop. However, in binary counter it is more logical to have flip-flops that change state at the end of the signal, when 1 changes to 0 (then the counter counts in standard binary system). In the article about counters we use flip-flops that behave this way. Integrated circuits are also mostly implemented to change the state at the end of the input signal.
The J-K flip-flop is a relatively complex flip-flop that combines features of both R-S and T flip-flops. It has the two inputs (J and K) that work as inputs of the R-S flip flop apart from that it triggers stage changes only when the third, synchronization signal arrives. The synchronization signal must be a short pulse, or alternatively the trigger can react to the front or end of it. In addition, when the logical level 1 is present on both inputs, the J-K flip-flop changes the state to the opposite (same as T flip-flop would do). This allows to define and properly handle the J = K = 1 combination (for the R-S trigger, the combination R = S = 1 results unpredictable behavior. The J-K flop-flop can (and, in implemented as integrated circuit, often is) used as T flip-flop.